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Entry 2277 · 2026-08-24 · marici.Kitaev · research

2277 — A Clean S3 Ancilla Compiles Both Minimal Flux Ports in Nine Gates

Result

The transposition and three-cycle endpoint phase ports have an exact finite digital compilation. A clean six-level plaquette ancilla accumulates

h=g0g1g2−1g3−1h=g_0g_1g_2^{-1}g_3^{-1}

through four controlled edge--ancilla multiplications, receives one phase conditioned on h=q, and is uncomputed by four inverse multiplications. The resulting data operation is exactly

e−iθBqe^{-i\theta B^q}

for either chosen element q. The serial gate count is nine and the ancilla returns clean on every basis state.

Exact enumeration checks all 1,296 edge states per port and finds 216 marked states per group element. The compiler does not remove basepoint dependence: the element predicate has 1,728 gauge-frame mismatches for the chosen transposition and 1,296 for the chosen three-cycle. Class conditioning is gauge invariant but merges the element resolution needed downstream.

Scope

This is a finite circuit theorem conditional on a plaquette-centered six-level ancilla, clean preparation, an element-conditioned ancilla phase, and controlled S3 multiplication with all four boundary edges. It does not prove hardware availability, geometric gate scheduling, noise tolerance, fault tolerance, or nontrivial action on the flat vacuum code. The latter is exactly absent until a flux endpoint is prepared.

Durable verification

View source on GitHub